A conventional video signal consists of a series of frames. Each frame contains a series of lines, and each line contains a plurality of pixels. Video line delays (or “video delay lines”) are needed to perform vertical format conversion and picture signal improvement. Other digital signal processing applications, such as audio filtering, and other computer related applications also require digital data to be delayed for a deterministic number of clock cycles. A typical line delay is constructed using a first-in-first-out queue (“FIFO”), with the line data fed into the input of the FIFO and clocked through to the FIFO output at a rate dependent on the amount of delay required and the FIFO size.
Typically, a Random Access Memory (“RAM”) is used in the FIFO when the amount of data is large enough to make the RAM implementation more practical than the alternatives (flip-flops or latches). For systems that have data written to and read from the RAM at times that are independent from each other, a dual-port RAM is typically used. A dual port RAM has independent read and write ports. Among other things, the dual ports allow data to be written to one RAM address and read from another simultaneously, which facilitates the delay design. However, a drawback of dual port RAMs is their silicon area. A dual port RAM can be 100% larger than a comparable single port RAM. Additionally, dual port RAMs are undesirably expensive.
The present invention is directed to overcoming this problem.